The present invention relates to a virtual machine system and, more particularly, to a virtual machine system adapted to perform an address translation at fast speeds in plural virtual machine systems.
A virtual machine system is a computer system to control one real machine as if plural computer machines (virtual machines) are present on one real computer machine (real machine). In the virtual machine system, a host control program (virtual machine control program: VMCP) controls a resource of one real machine, generating plural virtual machines (hereinafter referred to as VM) on the host control program. A memory of the VM is allocated at a predetermined area on a main storage of the real machine generated in accordance with an address translation table formed by the host control program on the main storage thereof. When a guest OS (guest operating system) that is an operating system on the VM implements a virtual memory control system, a virtual address space managing the guest OS is allocated at a region on the memory of the VM in accordance with an address translation table generated by the guest OS on the memory of the VM.
Accordingly, in order to allocate one page of a virtual memory of the guest OS at an area of the main storage of a real machine, an address translation is executed in two stages using the address translation table of the guest OS and the address translation table of the host control program. As shown in FIG. 2, a virtual address space 20 of the VM is translated to a real address space 40 of the VM by causing an address translation unit 30 to execute address translation using an address translation table 31. The real address space 40 of the VM is the same as a virtual address space 41 of the real machine in the host control program. Then the virtual address space 41 of the real machine is translated to a real address space 60 by causing an address translation unit 50 to execute address translation with an address translation table 51 of the host control program. As have been described hereinabove, the address translation is executed in two stages, thus allocating from the virtual address space 20 of the VM to the real address space 60 of the real machine. However, this delays address translation speed in the virtual machine system.
In order to make the virtual machine system to work at fast speeds, a mechanism for the two-stage address translation is implemented as a hardware mechanism, as has been discussed in "IBM System/370 Extended Architecture Interpretive Execution (SA22-7095-0) First Edition, January 1984."
The hardware mechanism for executing the address translation of the VM realizes [Virtual (V)=Real (R)] VM (preferred guest) as one of hardware facility, which is one mechanism capable of operating only one VM at fast speeds. In allocating the memory of the VM in the main storage of the real machine, this mechanism equalizes its address to a low-order address starting from zero of the main storage of the real machine, permitting a continuous permanent allocation. This may render the address translation and the paging process unnecessary, thus realizing a fast speed operation of the VM. Accordingly, only one [V=R]VM can be realized in the system by using the mechanism.
An alternative technique for fast speed operation is a resident VM technique for operating plural VMs at fast speeds. For example, as shown in FIG. 3, this technique permits a continuous permanent allocation on the main storage of the real machine other than a V=R region by providing a resident VM region in allocating the memory of the VM to the main storage of the real machine. An address of the main storage of the real machine in which the memory of the VM is allocated is equivalent to an addition of a first address in a region in which the resident VM is allocated to an address on the memory of the VM. Such resident VM does not require paging process by a host control program like [V=R]VM, thus allowing the address translation to be executed at fast speeds. As this technique for the fast speed processing is realized by a software means, there is required an address translation, more specifically, an address addition.
Conventional virtual machine systems are provided with a hardware mechanism for the fast speed processing, however, this mechanism is to execute only one VM ([V=R]VM) at fast speeds without any mechanism for executing plural VMs at fast speeds.
As a mechanism for executing plural VMs is one that realizes a function (resident VM) executing plural VMs at fast speeds to some extent using a one stage address translation mechanism. Although this mechanism is realized by a software means of a control program, a limit is produced upon efficiency in the fast speed processing.